1. Field of the Description
An enhanced modeling capability to predict photoresist (resist) profiles at any plane is described herein. This enhanced modeling capability addresses exposure energy separately from other factors, e.g. chemical effects of the resist.
2. Related Art
The resolution of optical projection lithography is generally described using Rayleigh's formula:R=k1*λ/NA where λ is the exposure wavelength, NA is the numerical aperture of the projection optics, and k1 is a constant depending on the lithographic process. As k1 decreases, the lithographic process becomes more difficult. Low k1 lithography (typically below 0.35) can result in pattern fidelity degradation, a narrow process window, and increased sensitivity to process variation. With a steadily shrinking k1 factor in advancing patterning technology generations, the benefit of photolithographic enhancement using Optical Proximity Correction (OPC) to compensate for imaging errors from diffraction and process effects is facing the challenge of an undesirable shrinking Usable Depth of Focus (UDOF).
To date, simulation for OPC model calibration has been conducted at a single image depth (single focus plane) in a process stack (e.g. resist, top/bottom anti-reflective coatings, hard mask) with a silicon substrate. Specifically, OPC only focuses on rendering the design result at the bottom of the resist (where wafer measurements are taken and then used for compact model calibration). As a result, any topography variation along the z direction in OPC has been ignored. Unfortunately, this simplistic approach can cause the predicted resist image to lose awareness of its full patterning integrity due to Resist Top Loss (RTL) or unacceptable SideWall Angles (SWA), thereby making it susceptible to failure upon etch. Note that the RTL is a relative term that describes the loss of height/depth of the photoresist.
For example, FIGS. 1A and 1B illustrate cross-sectional views of various features patterned in a resist layer 101, wherein some of those features exhibit relative RTL and unacceptable SWA. Specifically, FIG. 1A shows a feature 102 that has a top loss 103 (relative to an expected “top” 105) and an unacceptable SWA 104, whereas FIG. 1B shows a feature 112 that has a top loss 113 (relative to an expected “top” 114). When patterned resist layer 101 is subjected to etching, features 102 and 112 may cause an undesirable or unexpected patterning of the underlying layer 100. Unfortunately, as indicated above, neither RTL nor SWA information is currently collected by a conventional top-down SEM (Scanning Electron Microscope) metrology.
Complex patterning schemes and shrinking process margins, which are both inherent in low k1 processes, need more sophisticated verification checks. These more sophisticated verification checks may require traditional compact lithographic models to be augmented with information from rigorous models, which include 3-D descriptions of process behavior. However, the use of such rigorous models would take a significant amount of time. For example, using rigorous models for full-chip simulation on a 45 nm layer is estimated to take a commercial software tool approximately 3000 years on one CPU to complete. Thus, the TurnAround Time (TAT) of using rigorous models for full layout OPC and validation applications is unacceptable for commercial use.
Therefore, a need arises for an enhanced compact model that provides accurate resist profile information while ensuring a commercially reasonable run time.